1. Field of the Invention
The present invention relates to output buffers, and more particularly to a CMOS output buffer having a relatively constant output slew rate, independent of loading, due to a fast gate voltage error recovery.
2. Description of the Related Art
Conventional CMOS output buffers are sensitive to loading. That is, the output slew rate (or rise time) is a function of the capacitance connected to the buffer. The larger the capacitance, the slower the output slew rate (or rise time). If a very small capacitive load is connected to the output buffer, then the output slew rate may be very large, which can cause interference with adjacent circuitry. If a very large capacitive load is connected to the buffer, then the slew rate may be so low that at high data rates the output of the buffer will never reach its final value before switching again. Either condition is undesirable. Conventional CMOS output buffers also have some slew rate sensitivity to supply voltages.
A conventional CMOS buffer can be optimized to drive a particular load with a particular supply voltage. However, where the load and/or the supply voltage may vary (for example, where one device is used in a variety of applications), it would be desirable to have a CMOS output buffer which has a controlled and constant slew rate, which is relatively insensitive to loading or supply.